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M27V160
16 Mbit (2Mb x8 or 1Mb x16) Low Voltage UV EPROM and OTP EPROM
s
3V to 3.6V LOW VOLTAGE in READ OPERATION ACCESS TIME: 100ns BYTE-WIDE or WORD-WIDE CONFIGURABLE 16 Mbit MASK ROM REPLACEMENT LOW POWER CONSUMPTION - Active Current 30mA at 8MHz - Standby Current 60A
1 1 42 44
s s
s s
FDIP42W (F)
SO44 (M)
s s s
PROGRAMMING VOLTAGE: 12.5V 0.25V PROGRAMMING TIME: 50s/word ELECTRONIC SIGNATURE
42
- Manufacturer Code: 20h - Device Code: B1h DESCRIPTION The M27V160 is a low voltage 16 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage. It is organised as either 2 Mbit words of 8 bit or 1 Mbit words of 16 bit. The pin-out is compatible with a 16 Mbit Mask ROM. The M27V160 operates in the read mode with a supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges. The FDIP42W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written rapidly to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27V160 is offered in PDIP42 and SO44 packages.
1
PDIP42 (B)
Figure 1. Logic Diagram
VCC
20 A0-A19 15
Q15A-1
Q0-Q14 E G BYTEVPP M27V160
VSS
AI01898
March 2000
1/15
M27V160
Figure 2A. DIP Connections Figure 2B. SO Connections
A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11
1 42 2 41 3 40 4 39 5 38 6 37 7 36 8 35 9 34 10 33 M27V160 11 32 12 31 13 30 14 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22
AI01899
A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTEVPP VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11
1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 M27V160 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23
AI01900
NC A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTEVPP VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
Table 1. Signal Names
A0-A19 Q0-Q7 Q8-Q14 Q15A-1 E G BYTEVPP VCC VSS NC Address Inputs Data Outputs Data Outputs Data Output / Address Input Chip Enable Output Enable Byte Mode / Program Supply Supply Voltage Ground Not Connected Internally
DEVICE OPERATION The operating modes of the M27V160 are listed in the Operating Modes Table. A single power supply is required in the read mode. All inputs are TTL compatible except for VPP and 12V on A9 for the Electronic Signature. Read Mode The M27V160 has two organisations, Word-wide and Byte-wide. The organisation is selected by the signal level on the BYTEVPP pin. When BYTEVPP is at VIH the Word-wide organisation is selected and the Q15A-1 pin is used for Q15 Data Output. When the BYTEVPP pin is at VIL the Byte-wide organisation is selected and the Q15A-1 pin is used for the Address Input A-1. When the memory is logically regarded as 16 bit wide, but read in the Byte-wide organisation, then with A-1 at VIL the lower 8 bits of the 16 bit data are selected and with A-1 at VIH the upper 8 bits of the 16 bit data are selected.
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M27V160
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO (2) VCC VA9 (2) VPP Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage (except A9) Supply Voltage A9 Voltage Program Supply Voltage Value -40 to 125 -50 to 125 -65 to 150 -2 to 7 -2 to 7 -2 to 13.5 -2 to 14 Unit C C C V V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is -0.5V with possible undershoot to -2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range.
Table 3. Operating Modes
Mode Read Word-wide Read Byte-wide Upper Read Byte-wide Lower Output Disable Program Verify Program Inhibit Standby Electronic Signature E VIL VIL VIL VIL VIL Pulse VIH VIH VIH VIL G VIL VIL VIL V IH V IH VIL V IH X VIL BYTEVPP V IH VIL VIL X V PP V PP V PP X V IH A9 X X X X X X X X V ID Q15A-1 Data Out VIH VIL Hi-Z Data In Data Out Hi-Z Hi-Z Code Q14-Q8 Data Out Hi-Z Hi-Z Hi-Z Data In Data Out Hi-Z Hi-Z Codes Q7-Q0 Data Out Data Out Data Out Hi-Z Data In Data Out Hi-Z Hi-Z Codes
Note: X = VIH or VIL, VID = 12V 0.5V.
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VIH Q15 and Q7 0 1 Q14 and Q6 0 0 Q13 and Q5 1 1 Q12 and Q4 0 1 Q11 and Q3 0 0 Q10 and Q2 0 0 Q9 and Q1 0 0 Q8 and Q0 0 1 Hex Data 20h B1h
The M27V160 has two control functions, both of which must be logically active in order to obtain data at the outputs. In addition the Word-wide or Byte- wide organisation must be selected. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to
the output pins independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV.
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M27V160
Table 5. AC Measurement Conditions
High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V Standard 20ns 0.4V to 2.4V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V
AI01822
1N914
3.3k
Standard 2.4V
OUT CL
0.4V
CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol C IN COUT Parameter Input Capacitance (except BYTEVPP) Input Capacitance (BYTEVPP) Output Capacitance Test Condition VIN = 0V VIN = 0V VOUT = 0V Min Max 10 120 12 Unit pF pF pF
Note: 1. Sampled only, not 100% tested.
Standby Mode The M27V160 has a standby mode which reduces the active current from 20mA to 20A with low voltage operation VCC 3.6V, see Read Mode DC Characteristics table for details.The M27V160 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:
a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
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M27V160
Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70C or -40 to 85C; VCC = 3.3V 10%; VPP = VCC)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0V VIN V CC 0V VOUT VCC E = VIL, G = VIL, IOUT = 0mA, f = 8MHz, V CC 3.6V Supply Current E = VIL, G = VIL, IOUT = 0mA, f = 5MHz, V CC 3.6V Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL IOL = 2.1mA IOH = -400A 2.4 E = VIH E > VCC - 0.2V, VCC 3.6V VPP = VCC -0.3 0.7V CC 20 1 60 10 0.2VCC VCC + 1 0.4 mA mA A A V V V V Min Max 1 10 30 Unit A A mA
ICC
ICC1 ICC2 IPP VIL VIH (2) VOL VOH
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is VCC +0.5V.
System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the supplies to the devices. The supply current ICC has three segments of importance to the system designer: the standby current, the active current and the transient peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device outputs. The associated transient voltage peaks can be suppressed by complying with the two line out-
put control and by properly selected decoupling capacitors. It is recommended that a 0.1F ceramic capacitor is used on every device between VCC and VSS. This should be a high frequency type of low inherent inductance and should be placed as close as possible to the device. In addition, a 4.7F electrolytic capacitor should be used between VCC and VSS for every eight devices. This capacitor should be mounted near the power supply connection point. The purpose of this capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.
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M27V160
Table 8. Read Mode AC Characteristics (1) (TA = 0 to 70C or -40 to 85C; VCC = 3.3V 10%; VPP = VCC)
M27V160 Symbol Alt Parameter Test Condition -100 (3) Min tAVQV tBHQV tELQV tGLQV tBLQZ (2) tEHQZ (2) tGHQZ (2) tAXQX tBLQX tACC tST tCE tOE tSTD tDF tDF tOH tOH Address Valid to Output Valid BYTE High to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid BYTE Low to Output Hi-Z Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition BYTE Low to Output Transition E = VIL , G = VIL E = VIL , G = VIL G = VIL E = VIL E = VIL , G = VIL G = VIL E = VIL E = VIL , G = VIL E = VIL , G = VIL 0 0 5 5 Max 100 100 100 50 45 45 45 0 0 5 5 -120 Min Max 120 120 120 60 50 50 50 0 0 5 5 -150 Min Max 150 150 150 60 50 50 50 ns ns ns ns ns ns ns ns ns Unit
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP 2. Sampled only, not 100% tested. 3. Speed obtained with High Speed measurement conditions.
Figure 5. Word-Wide Read Mode AC Waveforms
A0-A19
VALID tAVQV tAXQX
VALID
E tGLQV G tELQV Q0-Q15 tGHQZ Hi-Z tEHQZ
AI00741B
Note: BYTEV PP = VIH.
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M27V160
Figure 6. Byte-Wide Read Mode AC Waveforms
A-1,A0-A19
VALID tAVQV tAXQX
VALID
E tGLQV G tELQV Q0-Q7 tGHQZ Hi-Z tEHQZ
AI00742B
Note: BYTEV PP = VIL.
Figure 7. BYTE Transition AC Waveforms
A0-A19
VALID
A-1 tAVQV BYTEVPP
VALID tAXQX
tBHQV Q0-Q7 tBLQX Hi-Z Q8-Q15 tBLQZ
AI00743C
DATA OUT
DATA OUT
Note: Chip Enable (E) and Output Enable (G) = VIL.
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M27V160
Table 9. Programming Mode DC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.5V 0.25V)
Symbol ILI ICC IPP V IL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = -2.5mA 3.6 11.5 12.5 E = VIL -0.3 2.4 Test Conditio n 0 V IN VCC Min Max 1 50 50 0.8 VCC + 0.5 0.4 Unit A mA mA V V V V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
Table 10. Programming Mode AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.5V 0.25V)
Symbol tAVEL tQVEL tVPHAV tVCHAV tELEH tEHQX tQXGL tGLQV tGHQZ (2) tGHAX Alt tAS tDS tVPS tVCS tPW tDH tOES tOE tDFP tAH Parameter Address Valid to Chip Enable Low Input Valid to Chip Enable Low VPP High to Address Valid VCC High to Address Valid Chip Enable Program Pulse Width Chip Enable High to Input Transition Input Transition to Output Enable Low Output Enable Low to Output Valid Output Enable High to Output Hi-Z Output Enable High to Address Transition 0 0 Test Condition Min 2 2 2 2 45 2 2 120 130 55 Max Unit s s s s s s s ns ns ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested.
Programming The M27V160 has been designed to be fully compatible with the M27C160. As a result the M27V160 can be programmed as the M27C160 on the same programming equipments applying 12.75V on VPP and 6.25V on VCC by the use of the same PRESTO III algorithm. When delivered (and after each erasure for UV EPROM), all bits of the M27V160 are in the '1' state. Data is introduced by selectively programming '0's to the desired bit lo-
cations. Although only '0's will be programmed, both '1's and '0's can be present in the data word. The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The M27V160 is in the programming mode when Vpp input is at 12.5V, G is at VIH and E is pulsed to VIL. The data to be programmed is applied to 16 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V 0.25V.
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M27V160
Figure 8. Programming and Verify Modes AC Waveforms
A0-A19 tAVEL Q0-Q15 DATA IN tQVEL BYTEVPP tVPHAV VCC tVCHAV E tELEH G
VALID
DATA OUT tEHQX
tGLQV
tGHQZ
tGHAX
tQXGL
PROGRAM
VERIFY
AI00744
Figure 9. Programming Flowchart
VCC = 6.25V, VPP = 12.5V
n=0
E = 50s Pulse NO ++n = 25 YES NO VERIFY YES Last Addr NO ++ Addr
FAIL
YES CHECK ALL WORDS BYTEVPP =VIH 1st: VCC = 5V 2nd: VCC = 3V
AI00901B
PRESTO III Programming Algorithm The PRESTO III Programming Algorithm allows the whole array to be programed with a guaranteed margin in a typical time of 52.5 seconds. Programming with PRESTO III consists of applying a sequence of 50s program pulses to each word until a correct verify occurs (see Figure 9). During programing and verify operation a MARGIN MODE circuit is automatically activated to guarantee that each cell is programed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE at VCC much higher than 3.6V provides the necessary margin to each programmed cell. Program Inhibit Programming of multiple M27V160s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27V160 may be common. A TTL low level pulse applied to a M27V160's E input and VPP at 12.5V, will program that M27V160. A high level E input inhibits the other M27V160s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E at VIH and G at VIL, VPP at 12.5V and VCC at 6.25V.
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M27V160
On-Board Programming The M27V160 can be directly programmed in the application circuit. See the relevant Application Note AN620. Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25C 5C ambient temperature range that is required when programming the M27V160. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27V160, with VPP = VCC = 5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = V IH) the device identifier code. For the STMicroelectronics M27V160, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0. Note that the M27V160 and M27C160 have the same identifier bytes. ERASURE OPERATION (applies to UV EPROM) The erasure characteristics of the M27V160 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 A. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 A range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27V160 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27V160 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27V160 window to prevent unintentional erasure. The recommended erasure procedure for M27V160 is exposure to short wave ultraviolet light which has a wavelength of 2537 A. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 30 W-sec/cm2. The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with 12000 W/cm2 power rating. The M27V160 should be placed within 2.5cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure.
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M27V160
Table 11. Ordering Information Scheme
Example: Device Type M27 Supply Voltage V = 3V to 3.6V Device Function 160 = 16 Mbit (2Mb x 8 or 1Mb x 16) Speed -100 (1) = 100 ns -120 = 120 ns -150 = 150 ns V CC Tolerance blank = 3.3V 10% X = 3.3V 5% Package F = FDIP42W (2) B = PDIP42 M = SO44 (2) Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Optio ns TR = Tape & Reel Packing M27V160 -100 X M 1 TR
Note: 1. High Speed, see AC Characteristics section for further information. 2. Packages option available on request. Please contact STMicroelectronics local Sales Office.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M27V160
Table 12. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
Symb A A1 A2 A3 B B1 C D D2 E E1 e eA eB L S K K1 N 9.40 11.43 2.54 14.99 50.80 15.24 1.45 mm Typ Min - 0.51 3.91 3.89 0.41 - 0.23 54.41 - - 14.50 - - 16.18 3.18 1.52 - - 4 42 Max 5.72 1.40 4.57 4.50 0.56 - 0.30 54.86 - - 14.90 - - 18.03 4.10 2.49 - - 11 0.370 0.450 0.100 0.590 2.000 0.600 0.057 Typ inches Min - 0.020 0.154 0.153 0.016 - 0.009 2.142 - - 0.571 - - 0.637 0.125 0.060 - - 4 42 Max 0.225 0.055 0.180 0.177 0.022 - 0.012 2.160 - - 0.587 - - 0.710 0.161 0.098 - - 11
Figure 10. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
A3 A1 B1 B D2 D S
N
A L eA eB C
e1
K
1
E1
E
K1
FDIPW-b
Drawing is not to scale.
12/15
M27V160
Table 13. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symb A A1 A2 B B1 C D D2 E E1 e1 eA eB L S N 42 2.54 14.99 50.80 15.24 mm Typ Min - 0.25 3.56 0.38 1.27 0.20 52.20 - - 13.59 - - 15.24 3.18 0.86 0 Max 5.08 - 4.06 0.53 1.65 0.36 52.71 - - 13.84 - - 17.78 3.43 1.37 10 42 0.100 0.590 2.000 0.600 Typ inches Min - 0.010 0.140 0.015 0.050 0.008 2.055 - - 0.535 - - 0.600 0.125 0.034 0 Max 0.200 - 0.160 0.021 0.065 0.014 2.075 - - 0.545 - - 0.700 0.135 0.054 10
Figure 11. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Outline
A2 A1 B1 B D2 D S
N
A L eA eB C
e1
E1
1
E
PDIP
Drawing is not to scale.
13/15
M27V160
Table 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
mm Symb Typ A A1 A2 B C D E e H L N CP 0.80 3 1.27 0.10 28.10 13.20 - 15.90 - - 44 0.10 Min 2.42 0.22 2.25 Max 2.62 0.23 2.35 0.50 0.25 28.30 13.40 - 16.10 - - 0.031 3 0.050 0.004 1.106 0.520 - 0.626 - - 44 0.004 Typ Min 0.095 0.009 0.089 Max 0.103 0.010 0.093 0.020 0.010 1.114 0.528 - 0.634 - - inches
Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Drawing is not to scale.
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M27V160
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com
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